This folder contains the experimental results from our ICCAD 2026 paper, "Optimal Transistor Level Layout of Single- and
Multi-Row Cells for 2nm and Beyond", by Stefan Hougardy, Benjamin Klotz, Malte Schürks, Armin Settels, and Tobias
Werner.

The directory ns3k-b contains the results for our modified ns3k data set. The directory ns3k-original contains our
results for the original ns3k data set. The files `results-ns3k-b.md` and `results-ns3k-original.md` provide an overview
of our results.

For latches, we provide both the results of the linear arrangement placer with full height subcells, and the block-based
branch-and-bound placer. For each of them, we provide results where M2 usage was allowed and forbidden (`-nom2` suffix).
We also provide symlinks `best` (for all cells) and `best-nom2` (for latches) pointing to the run with lowest cell area.
When comparing to the results of BonnCell in general rather than to specific algorithms, these results should be
preferred.

### Placement JSON files

In addition to the `.gds` layout, all layouts include a file `placement.json` containing a structural definition of the
FET placement. There are two relevant top-level entries in the JSON object contained in the file:  
`cellWidthInPCTracks` specifies the width of the cell, measured from the center of the dummy gate on the left boundary
to that on the right boundary.  
`fets` contains an array describing the placement of individual FETs. Each entry in the array is an object with the
following properties:
- `name`: The name of the FET in the SPICE netlist.
- `stack`: This indicates the "half circuit row" the FET is placed in. They are numbered from 0 to `2 * rows - 1` from
  the bottom to the top of the cell.
- `numFingers`: The number of fingers of the FET.
- `sheetSizePerFinger`: Sheet width of each individual finger. Always `0.02` in NS3K.
- `track`: The leftmost LTC track occupied by the FET. The LTC track immediately to the right of the left boundary has
  index 0.
- `leftContact`: `source` or `drain`, indicating whether the net on `track` is the source- or the drain net of the FET.
- `replacedFet` (optional): This is used when a FET is split into multiple smaller parts. `replacedFet` indicates which
  FET this "sub-FET" is a part of. The name specified in `name` does not appear in the SPICE netlist in this case and
  only refers to this part of the original FET.


Example:
```json
{
    "fets": [
        {
            "name": "1",
            "stack": 0,
            "numFingers": 1,
            "sheetSizePerFinger": 0.02,
            "track": 0,
            "leftContact": "source"
        },
        {
            "name": "2",
            "stack": 1,
            "numFingers": 1,
            "sheetSizePerFinger": 0.02,
            "track": 0,
            "leftContact": "source"
        }
    ],
    "cellWidthInPCTracks": 2
}
```
