<resource xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns="http://datacite.org/schema/kernel-4" xsi:schemaLocation="http://datacite.org/schema/kernel-4 http://schema.datacite.org/meta/kernel-4.1/metadata.xsd"><identifier identifierType="DOI">10.60507/FK2/TJNDMQ</identifier><creators><creator><creatorName nameType="Personal">Gogolou, Vasiliki</creatorName><givenName>Vasiliki</givenName><familyName>Gogolou</familyName><nameIdentifier SchemeURI="https://orcid.org/" nameIdentifierScheme="ORCID">0000-0003-3596-4814</nameIdentifier><affiliation>University of Bonn</affiliation></creator></creators><titles><title>Design of DEPFET front-end readout circuit</title></titles><publisher>bonndata</publisher><publicationYear>2026</publicationYear><subjects><subject>Engineering</subject><subject>Physics</subject></subjects><contributors><contributor contributorType="ContactPerson"><contributorName nameType="Personal">Gogolou, Vasiliki</contributorName><givenName>Vasiliki</givenName><familyName>Gogolou</familyName><affiliation>University of Bonn</affiliation></contributor></contributors><dates><date dateType="Issued">2026-08-28</date><date dateType="Created">2026-07-02</date><date dateType="Updated">2026-09-03</date></dates><resourceType resourceTypeGeneral="Dataset"/><sizes><size>13105</size><size>13085</size><size>2035</size><size>2137618</size><size>1034715</size><size>3115098</size><size>358</size><size>361</size><size>5654</size><size>408</size><size>6624</size><size>357</size><size>948392</size><size>865705</size><size>859394</size><size>414</size><size>6311</size><size>4540</size><size>1878</size></sizes><formats><format>text/csv</format><format>text/csv</format><format>text/csv</format><format>text/csv</format><format>text/csv</format><format>text/csv</format><format>text/csv</format><format>text/csv</format><format>text/csv</format><format>text/csv</format><format>text/csv</format><format>text/csv</format><format>text/csv</format><format>text/csv</format><format>text/csv</format><format>text/csv</format><format>text/plain</format><format>text/csv</format><format>text/csv</format></formats><version>1.0</version><rightsList><rights rightsURI="info:eu-repo/semantics/openAccess"/><rights rightsURI="http://creativecommons.org/licenses/by/4.0">CC BY 4.0</rights></rightsList><descriptions><description descriptionType="Abstract">This dataset contains numerical results generated from circuit simulations performed as part of NexGenRE ("Next-Generation Front End Readout Electronics for Particle Physics Experiments"), a Marie Sklodowska-Curie Post-Doctoral Fellowship project focused on developing next-generation readout electronics for precise and reliable data acquisition systems. The simulations investigate performance metrics including transimpedance gain, bandwidth, step response, output noise, power consumption, loop-gain behaviour, detector-capacitance sensitivity, switch timing, and temperature dependence for a differential readout integrated circuit for DEPFET pixel matrices.</description><description descriptionType="TechnicalInfo">Cadence Virtuoso, 23.1</description><description descriptionType="TechnicalInfo">Cadence Spectre, 23.1</description></descriptions><geoLocations/><fundingReferences><fundingReference><funderName>European Union</funderName><awardNumber>101209036</awardNumber></fundingReference></fundingReferences></resource>