Design of DEPFET front-end readout circuitdoi:10.60507/FK2/TJNDMQbonndata2026-09-031Gogolou, Vasiliki, 2026, "Design of DEPFET front-end readout circuit", https://doi.org/10.60507/FK2/TJNDMQ, bonndata, V1Design of DEPFET front-end readout circuitdoi:10.60507/FK2/TJNDMQGogolou, Vasiliki2026-07-02Cadence VirtuosoCadence Spectre101209036bonndataGogolou, VasilikiGogolou, Vasiliki2026-08-28EngineeringPhysicsThis dataset contains numerical results generated from circuit simulations performed as part of NexGenRE ("Next-Generation Front End Readout Electronics for Particle Physics Experiments"), a Marie Sklodowska-Curie Post-Doctoral Fellowship project focused on developing next-generation readout electronics for precise and reliable data acquisition systems. The simulations investigate performance metrics including transimpedance gain, bandwidth, step response, output noise, power consumption, loop-gain behaviour, detector-capacitance sensitivity, switch timing, and temperature dependence for a differential readout integrated circuit for DEPFET pixel matrices.<a href="http://creativecommons.org/licenses/by/4.0">CC BY 4.0</a>Gogolou_DEPFET-frontend-readout_Readme.txttext/plainAFE_SDC_before_and_after_ADC_switch.csvtext/csvAFE_SDC_GAIN_PVT.csvtext/csvAFE_SDC_PHASE_PVT.csvtext/csvAFE_SDC_PSD_OUT.csvtext/csvAFE_SDC_step_response.csvtext/csvAFE_SDC_switch_signals.csvtext/csvAFE_TIA_BW_Cd_sweep.csvtext/csvAFE_TIA_BW_temp_sweep.csvtext/csvAFE_TIA_GAIN_33k_10f.csvtext/csvAFE_TIA_GAIN_IRN_temp_sweep.csvtext/csvAFE_TIA_GAIN_PVT.csvtext/csvAFE_TIA_GAIN_temp_sweep.csvtext/csvAFE_TIA_IN.csvtext/csvAFE_TIA_OUT.csvtext/csvAFE_TIA_OUT_step_response.csvtext/csvAFE_TOTAL_PWR_temp.csvtext/csvdata_dictionary.csvtext/csvsimulation_parameters.csvtext/csv